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STB90NF03L
N-CHANNEL 30V - 0.0056 - 90A D2PAK LOW GATE CHARGE STripFETTM POWER MOSFET
TYPE STB90NF03L
s s s s s
VDSS 30 V
RDS(on) < 0.0065
ID 90 A
TYPICAL RDS(on) = 0.0056 TYPICAL Qg = 35 nC @ 5V OPTIMAL RDS(on) x Qg TRADE-OFF CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED
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DESCRIPTION This application specific Power Mosfet is the third generation of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance.
D2PAK
INTERNAL SCHEMATIC DIAGRAM
s
APPLICATIONS SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID ID IDM (q) PTOT Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Storage Temperature Max. Operating Junction Temperature Value 30 30 18 90 65 360 150 0.73 - 55 to 175 Unit V V V A A A W W/C C
(q) Pulse width limited by safe operating area
October 2001
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THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 1 62.5 300 C/W C/W C
ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 18 V Min. 30 1 10 100 Typ. Max. Unit V A A nA
ON (1)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10V, ID = 45 A VGS = 5V, ID = 45 A Min. 1 0.0056 0.007 0.0065 0.012 Typ. Max. Unit V
DYNAMIC
Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 45 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 40 2700 860 170 Max. Unit S pF pF pF
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ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 15V, ID = 45 A RG = 4.7 VGS = 4.5 V (see test circuit, Figure 3) VDD = 24V, ID =90A,VGS = 5V Min. Typ. 30 200 35 10 18 47 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol td(off) Parameter Turn-off-Delay Time Test Conditions VDD = 15V, ID = 45 A, RG = 4.7, VGS = 4.5 V (see test circuit, Figure 3) Min. Typ. 50 Max. Unit ns
tf
Fall Time
105
ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (1) VSD (2) trr Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time ISD = 90 A, VGS = 0 ISD = 90 A, di/dt = 100A/s, VDD = 15V, Tj = 150C (see test circuit, Figure 5) 80 Test Conditions Min. Typ. Max. 90 360 1.3 Unit A A V ns
Qrr IRRM
Reverse Recovery Charge Reverse Recovery Current
90 2.5
nC A
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedence
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Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
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STB90NF03L
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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TO-263 (D2PAK) MECHANICAL DATA
mm MIN. A A1 B B2 C C2 D E G L L2 L3 4.4 2.49 0.7 1.14 0.45 1.21 8.95 10 4.88 15 1.27 1.4 TYP. MAX. 4.6 2.69 0.93 1.7 0.6 1.36 9.35 10.4 5.28 15.85 1.4 1.75 MIN. 0.173 0.098 0.027 0.044 0.017 0.047 0.352 0.393 0.192 0.590 0.050 0.055 inch TYP. MAX. 0.181 0.106 0.036 0.067 0.023 0.053 0.368 0.409 0.208 0.624 0.055 0.068
DIM.
D
A
C C2 DET AIL "A"
DET AIL "A" A1 B2 B
E
G
L2
L
L3
P011P6/E
A2
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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